The present application relates to data communications and more particularly to a network interface configured to support first-in, first-out (FIFO)-type accesses as well as static random access memory (SRAM)-type accesses to its buffer memory.
In a data communications network, such as an Ethernet (IEEE 802.3) network, a network controller chip provides interface between a local bus of a computer system and network media. The network controller has buffer memories provided between. a system memory interface and a media interface for temporarily storing data transferred between a system memory and a communications network. In particular, a receive buffer memory accumulates receive data supplied from the network, before transferring the data to the system memory, whereas a transmit; buffer memory is involved in transferring transmit data from the system memory to the network.
Some of computer systems utilize FIFO buffers, whereas other systems use static random access memory (SRAM) buffers. Therefore, to support compatibility with the systems having FIFO-type buffer memory access as well as with the systems having SRAM-type buffer memory access, it would be desirable to provide a network controller having a buffer memory accessible in a random access manner and in a FIFO manner.
The present invention! offers a novel method of providing a host with assess to a memory in FIFO and SRAM modes of operation. The method includes decoding whether the host issues a SRAM-type access request or a FIFO-type access request to perform access to the memory. In response to the FIFO-type access request, pointers to the memory are controlled so as to perform sequential addressing of the memory. In response to the SRAM-type request, the pointers are controlled so as to perform random access addressing of the memory.
In accordance with one aspect of the invention, a network interface controlled by a host comprises a host interface for providing interface to the host, a buffer memory for temporarily storing data, and an access control system for providing the. host with SRAM-type access to the buffer memory in a SRAM mode of operation, and with FIFO-type access to the buffer memory in a FIFO mode of operation.
In a preferred embodiment, the access control system comprises a pointer control mechanism for producing pointers to locations of the buffer memory to be accessed in the SRAM mode and FIFO mode. The pointer control mechanism may comprise a decoder for detecting requests from the host for the SRAM-type access and the FIFO-type access. A pointer control circuit may be responsive to a select signal from the decoder for providing sequential addressing of the buffer memory in the FIFO mode. In response to an address signal from the host, the pointer control circuit provides random-access addressing of the buffer memory in the SRAM mode.
The pointer control circuit may comprise a select multiplexer having a FIFO-mode input and a SRAM-mode input. An incrementing circuit coupled to the FIFO-mode input of the multiplexer may be supplied with the select signal, which also may be provided to a control input of the multiplexer. The SRAM-mode input may be supplied with the address signal.
In accordance with another aspect of the invention, a communication device controlled by a host comprises a transmit buffer for temporarily storing transmit data, and a receive buffer for temporarily storing receive data. A pointer control mechanism controls write pointers to locations of the transmit buffer so as to enable the host to write the transmit data in a random access manner and in a FIFO manner. Read pointers to locations of the-receive buffer are controlled so as to enable the host to read the receive data in a random access manner and in a FIFO manner.
The pointer control mechanism may comprise a write pointer control circuit for producing the write pointers, and a read pointer control circuit for producing the read pointers. In response to the FIFO-type access request from the host, the write pointer control circuit and read pointer control circuit may be supplied with the select signal to provide sequential addressing of the transmit buffer and the receive buffer. In response to the SRAM-type access request, the write pointer control circuit and read pointer control circuit are supplied with the address signal to provide random-access addressing of the transmit buffer and the receive buffer.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.